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Technology TermsA -------------------------------------------------------------------------------- ACA (Anisotropic Conductive Adhesive) Adhesive with conducting filler particles where the electrical
conductivity is achieved only in z-direction under mechanical pressure. B -------------------------------------------------------------------------------- Ball bump
bonding Ball bump
bonding places a gold ball bump on an active circuit prior to bonding the wedge
bond of the associated interconnecting wire. Used for stacked die, reverse
bonding and multi-chip scale packages. Ball Grid
Array (BGA) Type of chip package. An integrated circuit surface-mountpackage with an area array of solder balls that are
attached to the bottom side of a substrate with routing layers. Bare Die Non-encapsulated
silicon chip in singulated form BCB Benzocyclobutene Polymer dielectric from Dow Chemical used for wafer-level
redistribution. BGA Ball Grid Array IC single or multichip package with an area of solder balls attached
on the buttom side of a package. Bond
deformation The change in the form of the lead produced by the bonding tool,
causing plastic to flow in making the bond. Bond
force Vertical force on the bonding tool (capillary) during the bonding
cycle. Bond Line
Thickness (BLT) Determines the average thickness of the bonding material (epoxy,
solder). Bond pad A metallized region on the top surface of
semiconductor die via which electrical connection to an external circuit is
made by means of a bond wire. BLT (Bondline
Thickness) The thickness of adhesive between chip and substrate. BT (Bismaleimide Tnazine) High temperature organic substrate material mainly used for overmolded ball grid arrays (BOA). Bump chip A chip
that has on its termination pads a bump of solder or other bonding material
that is used to bond the chip to external contacts. C -------------------------------------------------------------------------------- C4 (Controlled Collapse Chip Connection) The
classical flip chip technique from IBM using evaporated Pb-base
solder. Capillary
(HDH) A hollow
bonding tool used to guide the bonding wire and to apply force to the wire
during the bonding cycle. Carrier
(FAB) Holds the strips (leadframes) for the
transfers. Cassette Carrier
for wafers, mounted on wafer frames. CBGA (Ceramic Ball Grid Array) Ball grid array using a ceramic carrier/wiring board. CCC (Ceramic Chip Carrier) Chip
carrier with ceramic wiring board. CCGA (Ceramic Column Grid Array Area
array component with ceramic wiring board using solder colunms
of high lead solder alloy instead of eutectic solder balls. Chip See Die Chip on
Board (COB) A hybrid
technology that exclusively employs face-up-bonded chip devices interconnected
to the substrate in a conventional manner, i.e., by flying wires. A generic
term for mounting an unpackaged silicon die directly
onto the PCB. Chip
Scale Packaging (CSP) Small-footprint
integrated circuit packages, sometimes defined as 1.2
times the die size; more appropriately refers to array packages nearly the same
size as the chips they contain. CLCC (Ceramic Leaded Chip Carrier) Surface
mount technology (SMT) package made in cofired
ceramic with leads e.g. J-formed leads. COB (Chip
On Board) Assembly of one or more bare dice on a substrate with electrical
interconnection by wire bonding. COF (Chip On Flex) Special case of chip on board (COB) where the substrate is flexible
e.g. polyimide. Consumable Material for one-time use, e.g. gold wire, epoxy. Controlled
Collapse Chip Connection (C4) The most common example of solder-bump-based flip chip technology. Cp See
Process Capability Cpk See
process capability index CSP (Chip Size Package or Chip Scale Package) After
packaging the component size is roughly the die size. Curing
(CU) Process step for the hardening of epoxy. D -------------------------------------------------------------------------------- DCA
Direct Chip Attach Mounting
bare dice directly on the wiring board in chip on board (COB) or flip chip on
board technology. Die A small
piece of silicon wafer, bounded by adjacent scribe lines in horizontal and vertical
directions, that contains the complete device being manufactured. Also called chip
and microchip and plural is called “dice.” Die
Bonder (DB) Picks,
places and bonds chips onto strips, substrates or leadframes,
sometimes referred to as die attach. Die
Attach The process of attaching the die to the substrate or leadframe by using a specified type of epoxy adhesive (or
solder, glass flit, or using eutectic bonding). Dicing The separation of a semiconductor wafer into individual dice normally
performed by a saw with a rotating blade with embedded diamond particles. Die
Bonding The attachment of an integrated circuit chip to a substrate or header. DIP Dual
In-line Package is the traditional buglike packages
that have anywhere from 8 to 40 legs, evenly divided on two opposite sides of
the package. Dip Fluxing Dip fluxing is a processing technique that allows tighter pitch components to be attached to the circuit board without the use of solder. Devices like flip chip and WLCSPs in the 0.3mm up to 0.5 mm pitch range use this approach. The part is placed into a flux material to clean off the oxides and then placed onto the circuit board eliminating the need for solder printing. Discrete A device or component that has a single function, such as a diode or
transistor. E -------------------------------------------------------------------------------- Epoxy
Seal A method of nonhermetically sealing a lid to
a package. ESD (Electro- Static Discharge) Charge
that when created can damage electronic components. Eutectic
Process One of the various processes for attaching a die to a leadframe using an alloy with a minimized melting point. F -------------------------------------------------------------------------------- Flip Chip Flip chip
interconnect technology pertains to the mounting of a chip with its active side
facing the substrate with simultaneous interconnection via bumps. Flip Chip
in Package (FCIP) Can be a single chip package or multichip module. Flip Chip
on Board (FCOB) Bare
single chip or multiple chips mixed with other components on a board. FBGA Fine-Pitch Ball Grid Array Ball grid array with a fine pitch of 0.5 mm. FCBGA Flip Chip BGA Ball grid array type carrier using flip chip in package. FCIP (Flip
Chip In Package) Flip chip
technology used on a module carrier, e.g. on a ball grid array (BOA) or chip scale
package (CSP) substrate, or in a molded leadframe
package (instead of flip chip assembly on the main board). FCOB (Flip Chip On Board) Flip chip
assembly on the main system board. Flux A
material used to promote fusion or joining of metals in soldering and brazing.
In soldering, a material that breaks down surface oxides. FR4 Standard
printed circuit board (PCB) material (Flame
Retardant composition 4) G -------------------------------------------------------------------------------- No Items H -------------------------------------------------------------------------------- HALT
(Highly Accelerated Life Test) Stress test by accelerated aging, e.g. in temperature and vibration,
for reliability analysis. HASL (Hot Air Solder Leveling) Standard
surface finish (solder on copper) of printed circuit boards
(PCB) for surface mount technology (SMT). HAST (Highly Accelerated Stress Test) Stress test by accelerated aging,
e.g. in damp heat atmosphere, for reliability analysis. HDI (High Density Interconnect) Printed circuit board (PCB) substrate in fine-line multilayer
technology e.g. build-up technology with micro vias. Hermetic
Sealing Air-tight
seal designed to secure electronic components from any external factors that
could impact its functioning and workable lifetime. High Temp
Co-Fired Ceramics (HTCC) "High-temperature
co-fired ceramics (HTCC)" are primarily a multi-layered ceramic material
used as inserts in glass-to-metal packages. Complete ceramic packages can be
built. Two or more layers of ceramic tape with thicknesses ranging from 5 to 25
mm are co-fired at temperatures of more than 1000 degrees Celsius. The ceramic
tape layers consist of aluminum oxide ceramic, tungsten and molymanganese
and have metallized circuit patterns. Hybrid
Package A hybrid
package, also known as a microelectronic package, a metal wall package, a flat
pack or a glass-to-metal package, refers to the hermetically sealed packaging
of electronic components within one container. I -------------------------------------------------------------------------------- Integrated
circuit (IC) Chip, device. Adhesive
with conducting filler particles e.g. Ag-epoxy leading to isotropic electrical conductivity due to the contact of conducting particles. Interconnection The
conductive path required to achieve electrical connection between a circuit
element and the rest of the circuit. K -------------------------------------------------------------------------------- KGD (Known Good Die) A tested bare chip that has the same level of performance,
reliability, and quality as its packaged version. Typically used
in multichip modules. L -------------------------------------------------------------------------------- Lab-on-a-chip:
A small chip (often the size of a credit card) containing microfluidic channels narrower than a human hair. They take advantage of the
properties of liquids and gases to separate and better allow microsensors to analyze their constituent elements. LCC (Leaded Chip Carrier) Chip
carrier for surface mount technology with leads e.g. J-formed leads. LCCC (Leadless
Ceramic Chip Carrier) Ceramic
chip carrier for surface mount technology with side contacts running into lands
at the bottom of the package. LOC See Lead On Chip The curve
or arc of the wire between the attachment points at each end of a wire bond. Production
unit, collection of carriers or a batch of wafers processed at the same time. LLCC Leadless Chip Carrier Chip
carrier for surface mount technology with side contacts running into lands at
the bottom of the package. LTCC (Low Temp Co-fired Ceramic) LTTC allows
passive components such as resistors, inductors and capacitors to be embedded
into a multi-layer, integrated module by co-firing special ceramic tapes at
temperatures below 900 degrees Celsius. M -------------------------------------------------------------------------------- MCM See
Multichip Module Mean Time
Between Failure (MTBF) The average time during which the equipment performed its intended
function between failures; productive time divided by the number of failures
during that time.
See Failure Mean Time
To Repair (MTTR) The
average time required to correct a failure and to return the equipment to a
condition in which it can perform its intended function. The sum of all repair
time incurred during a specified period (including equipment and process test
time, but excluding maintenance delay) divided by the number of failures during
that period. Metallization A film pattern of conductive material deposited on a substrate to interconnect
electronic components, or the metal film on the bonding area of a substrate
that becomes a part of the bond and performs both an electrical and a
mechanical function. Micro
Electromechanical Systems (MEMS) A
technology that combines computers with tiny mechanical devices such as
sensors, valves, gears, mirrors and actuators embedded in semiconductor chips. Microfluidic Channels Microscopic channels narrower than a human hair (about 100 microns
wide) that take advantage of the properties of fluids to separate them. A main
component of lab-on-a-chip devices. Micron
(µm) Unit of length equal to one millionth of a meter. Conversion: 25.4 microns equals
0.0254mm = 0.001” = 1 mil = 1,000 microinches. Mil One-thousandth of an inch. Equal to 25.4 microns. Mold Third-party
equipment used to encapsulate semiconductor devices on the leadframe
with a thermosetting plastic. Multichip
Module (MCM) A
packaging approach based on the interconnection of multiple bare die on a
single substrate or printed circuit board (PCB) technology, often fine-line multilayer technology (high density interconnect, sequential build-up) Multichip
Package (MCP) An MCP
contains a few bare chips per package, and they can be arranged either
side-by-side or stacked on top of each other. MCPs
typically do not include discrete or passive components. MCP Multi-Chip Package Through-hole
or surface mount package containing two or more dice. MCM Multi-Chip Module Assembly of two or more bare dice on a substrate by any bonding technology. MCM-C MCM on a
Ceramic substrate Multichip
module using high temperature cofired ceramic (HTCC),
low temperature cofired ceramic (LTCC) or multilayer thickfihn substrate technology. MCM-D MCM on a
Deposited (metal dielectric) substrate Multichip module using layer deposition technology, e.g. physical
vapor deposition (PVD), on ceramic or silicon substrates. N -------------------------------------------------------------------------------- Nanotechnology:
The creation and use of objects at the nanoscale,
up to 100 nanometers in size. O -------------------------------------------------------------------------------- No Items P -------------------------------------------------------------------------------- Passivation The formation of an insulating layer directly over a circuit or
circuit element to protect the surface from contaminants, moisture or
particles. PCB See Printed
Circuit Board Photolithography
Photography
is the best analogy to describe the photolithography process. The stepper is
like a photographic enlarger where a light source projects an image through a
lens system onto photographic paper. The machine used to do all of this is
called a "stepper" because it literally does one die or a few die at
a time, then steps to the next die or set of die until it has exposed the
entire wafer. Photomask
Also
known as a "reticle" or "mask,"
this glass plate contains the patterns used for photolithographic manufacture
of integrated circuits. Photoresist A
photoactive film also known as "resist." Liquid photoresist
is applied to a wafer to create a thin, uniform film. This film reacts with
light energy from the stepper to define a circuit or component pattern on the
substrate. Pick and
Place (P&P) Module on
a die bonder; plucks chips from a wafer and places them on leadframes. Pitch or
lead pitch The
distance between the center of one lead to the center
of an adjacent lead. Plasma
Cleaning (PLCL) Third-party
equipment for cleaning purposes; uses ionized gas to remove residues. Power
devices Semiconductor
devices designed to handle high voltages and current. Power devices usually
have a high level of heat dissipation and therefore are often soldered to a heatsink. Printed
Circuit Board (PCB) A flat plate or base of insulating material bearing a pattern of
conductive material. It becomes an electrical circuit when components are attached and
soldered to it. Also simply called “board” or ”printed
wire board” (PWB). Probe
damage Any damage to the wafer surface caused by mechanical probing or
measurement. Process
Capability (Cp) Statistical
process control; the ratio of the tolerance limits (specification window or upper
specification minus the lower specification) of a process to the natural
variation of that process (estimated by six times the standard deviation of the
process output) Process
Capability Index (Cpk) Statistical
process control; a measure of process performance similar to process capability
(Cp), but adjusted for any variation of the average process output from the
stated target value for the process. PTH Pin-Through-Hole or Plated-Through-Hole A method
of obtaining electrical connection between components and substrate by soldering
component leads (or pins) inserted in plated through-holes. PWB Printed Wiring Board. A substrate of epoxy glass or other (basically organic) material on
which a pattern of conductive traces is formed to interconnect the components
that will be mounted upon it. Q -------------------------------------------------------------------------------- Quad Flat
Pack (QFP) A plastic or ceramic package with leads that project down and away
from all four sides of a square package. Standard surface mount technology (SMT) package R -------------------------------------------------------------------------------- Recipe
transfer - Wire bond Full recipe transfer via disk or host to ensure that the same recipe
(process) is used on all machines. A recipe created on one machine can be used on any other
equipment without a new setup. RF
Devices A device that generates a signal in the RF bandwidth. S -------------------------------------------------------------------------------- Set up
time Time it
takes to prepare a machine for a product or process. Self-assembly:
A
bottom-up assembly method by which individual components of a structure come
together, usually by bouncing around in a solution or gas. They connect to each
other based on their structural (or chemical) properties. Small
Outline Integrated Circuit (SOIC) Package type for surface mounting. Smart
Card (SC) A type of
chip card; it is a plastic card embedded with an integrated circuit (IC) that
stores and transacts data between users. Typically used for
phone cards, bankcards, identification cards, etc. In the semiconductor
industry, it can be considered as a package type. SMD (Surface Standard
component for surface mount technology (SMT). SMT (Surface Technology
where packaged components are mounted and soldered on top of a printed wiring
board (no pin-through hole). Snap
curing Fast curing process for snap-cure epoxy. Soft
Solder A metal alloy with a melting point below 450 degrees Celsius. Soft
Solder Dispenser (SSD) Module on
a soft solder die bonder for dispensing a solder pattern in a single shot. Soft
Solder Process Processes for soldering a die to a leadframe
through use of an alloy with a melting point below 450 degrees Celsius. SOIC See Small
Outline Integrated Circuit Standard
Deviation A measure of the spread of the process output or the spread of a
sampling statistic from the process (represented by the Greek letter sigma). Stud Bump
Bonding Flip chip
process using isotropic conductive adhesive ( combination with Au stud bumps. Substrate A material which
serves as the base for the mechanical and electrical connections of ICs (wiring
board). SOC System On a Chip A highly
integrated device composed of multiple functional blocks, including on-chip memory
and a processor (complete system in one IC). System-in-Package
(SiP) An SiP is comprised of one or few bare chips as well as the
associated discrete and passive components, all integrated into a single
package and functions as an electronic system. Functions include analog,
digital, optical, RF and MEMS (multichip module which is a subsystem in a
package). T -------------------------------------------------------------------------------- Tape
Automated Bonding (TAB) A method
for establishing an electrical interconnection between a die and a substrate
through use of conductors on flex tape that are
mass-bonded to bumps on the integrated circuit in a single operation. Thermocompression bonding A process involving the use of pressure and temperature to join two
materials by interdiffusion across the boundary. Thermosonic bonding A
high-yield interconnect process that uses heat and ultrasonic energy to form a
metallurgical bond between the wires and metal pads on an integrated circuit
and by means of heat and ultrasonic scrubbing of the wire on the pad U -------------------------------------------------------------------------------- UBM (Under Bump Metallurgy or Under Bump
Metallization) Additional
metallization applied on the pads of the wafer prior to the bumping. Units Per Hour (UPH) The
number of units a machine produces per hour. Underfill Encapsulant material typically deposited between a flip chip device and substrate
used to reduce the mechanical stress resulting from a mismatch in the
coefficient of thermal expansion (CTE) between the device and the substrate. Ultrasonic
The
bonding of wires to metal pads on an integrated circuit (and substrate resp. Bonding
leadframe) by means of a pressing mechanism at
ambient temperature ultrasonically vibrating at a higher frequency of >10
kHz. V ------------------------------------------------------------------------------ No items W -------------------------------------------------------------------------------- Wafer
Handler (WH) Module on
die bonder; loads wafers out of a wafer cassette and passes them to the picking
position. Wafer
Level Packaging (WLP) Wafer
level packaging is defined as the complete packaging at wafer level. The WLP
process must provide the complete packaging solution with no additional processing
at the die level, neither during production nor assembly. The most common ball pitch for WLCSP are 0.5mm and 0.4mm. 0.3mm pitch is showing emerginf interest Wafer
Mapping (WM) Representation
of usable and unusable die contained on a wafer; stored in a file. Wafer
Mapping Conversion Package (WMCP) Data
conversion from various prober formats to die bonder format. Wire
Bonder (WB) Equipment
that connects the contact pads of the device with the leads of the substrate. The most common method of making an electrical connection from a
die to a substrate. The wire is bonded to the die and substrate by
thermal compression and/or ultrasonic welding. Wires are typically made of
gold, aluminum or copper. Wire
Bonding The
primary method of electrically connecting a die to a package via wire loops.Technology for electrically connecting a die to a leadframe or substrate by bonding thin Au or Al wires with
a typical wire thickness of 25 microns WLP (Wafer Level Packaging) Additional
wafer processing step to produce a chip size package (CSP), e.g. by redistribution
technology and solder balling. X -------------------------------------------------------------------------------- No Items Y -------------------------------------------------------------------------------- No Items Z -------------------------------------------------------------------------------- |