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Technology Papers
Abstract :: This paper presents a systematic development of optimal no flow process underfill parameters compatible with four commercially available fluxing underfills. A novel hybrid process was developed that combines a capillary flow dynamic with no-flow fluxing underfills. The impact of the dispensing pattern on void formation is determined. Experiments are conducted to investigate the dispense pattern, placement speed and the impact of the placement process on interconnect yield further investigating the dispense pattern, placement force, and dwell time. A dispensed line pattern location and chip placement study is conducted to determine how voiding is affected by the position of the dispensed line in relation to the side of the die. The results of these experimental studies are used to select an optimal placement process for the materials. Reflow profile parameters are investigated using a parametric approach. The results of these initial studies are used to choose an optimal process for the materials. Test boards are assembled according to the optimal process for each material, and air to air thermal cycle, AATC, thermal cycling test is performed to qualify the assemblies. The newly developed edge patterned hybrid no-flow process has resulted in near void-free assemblies capable of passing 2000 cycles without an electrical failure for the -40 to 125 °C AATC reliability test.
NEAR VOID FREE HYBRID NO-FLOW UUNDERFILL FLIP CHIP PROCESS TECHNOLOGYIndex Terms: No-flow underfill, area array, flip chip, process optimization, void free, electronics packaging. Request This Paper
Abstract :: Wafer-level underfill has the potential to substantially increase the implementation and usage of flip chip technology in the electronics industry. The development of wafer-level underfills can bring the financial benefits of wafer-level processing to flip chip assembly and packaging. In order to realize these benefits, the wafer-level flip chip process should be transparent to standard assembly lines.
FLIP CHIP PROCESSING USING WAFER-APPLIED UNDERFILLSExperimental studies have identified a number of process-related defects, including underfill voids, underfill outgassing, and die misalignment resulting from the solid to liquid transition of the wafer applied underfills and their associated surface tension. In the current study, aspects of assembly processing that relate to wafer-level flip chip assembly quality are examined. A parametric study of the effect of underfill coating uniformity on assembly quality and underfill voiding is presented. To address the surface tension driven die misalignment, a method is explored for reducing die misalignment through the use of fillet-constraining solder mask patterns. In addition, a theoretical description of the forces acting on a wafer-level flip chip die is developed to better understand the influence of process and design parameters on assembly yield. Request This Paper
Abstract :: A comprehensive study is performed investigating the influence of plasma pretreatment on assembly yield for solder flip chip in package assemblies and chip scale package (CSP) assembly to SIP modules. In addition, a detailed reliability screening is performed on the assemblies to assess the impact of pre assembly plasma treatment on long term reliability of the assemblies. Various plasma treatment techniques and two substrate surface finishes are included in the experimental analysis. The flip chip and CSP devices are underfilled with fast flow, snap cure underfill material. Baseline assemblies without plasma pretreatment are tested for comparison. The test vehicles are subjected to liquid to liquid thermal shock or air to air thermal cycle testing and analyzed using electrical test, CSAM, X-ray, and microsectioning.
EFFECTS OF PLASMA PRETREATMENT ON FLIP CHIP AND CSP SUBSTRATE LEVEL ASSEMBLY YIELD AND RELIABILITYVisual inspection of the plasma treated samples revealed higher more uniform fillet shapes especially in the corners of the components compared with the untreated devices. CSAM analysis indicated no significant difference between the plasma treated and non-plasma treated samples in terms of underfill uniformity and void formation during processing. The flow times for the plasma treated flip chip samples were 12 to 20 percent faster than the non-plasma treated samples. The flow times for the plasma treated CSPs were 55% faster than the flow times for the untreated samples. As for flip chip reliability differences, the plasma treated test vehicles with Au finish had the highest reliability with a 70% improvement over untreated samples. In contrast, the untreated flip chip assemblies with an OSP finish had 78% higher reliability compared with the plasma treated counterpoints. For the CSP components, the reliability of the components were generally the same as the non-Plasma treated samples. Key Words: Plasma, Underfill, Flip Chip, Reliability, Yield Request This Paper
Abstract :: Demands on solder bump interconnects have increased in modern electronics this is characterized by high density, small size and fine pitch devices. In solder bump interconnects, solder wetting onto bond pads is the key factor that determines the interconnect process yield and the solder joint reliability. Solder wetting involves various physical phenomena such as a surface tension imbalance, viscous dissipation, molecular kinetic motion, chemical reactions and diffusion. In this paper, an experimental study on solder wetting dynamics will be presented along with an analytical predicting solder ball wetting. The effects of solder reflow process parameters and bonding materials will be discussed, as they relate to the physics of solder wetting and ultimately the interconnect process yield and solder joint reliability. The experimental setup consists of a high-speed image acquisition system and a temperature chamber which were used to measure the time dependent behavior of molten solder spheres onto bond pads under an isothermal condition. The solder materials investigated are eutectic tin-lead solder and lead-free 95.5Sn-4.0Ag-0.5Cu solder. The wetting dynamics of the solder materials were investigated on Cu, Cu/OSP, and Cu/Ni/Au bond pads, with several different flux systems, at different environmental temperatures and with various solder sphere sizes. The experimental observations indicate that the wetting dynamics clearly depend on temperature, solder materials and substrate metallization but do not depend significantly on the flux system or the solder sphere size.
EXPERIMENTAL WETTING DYNAMICS STUDY OF EUTECTIC AND LEAD-FREE SOLDERS VARYING FLUX, TEMPERATURE AND SURFACE FINISH METALLIZATIONMoreover, this research develops an analytic methodology based on solder wetting dynamics, that can be used to predict solder interconnect formation during electronics assembly. The major benefit of such an advanced process model is that it enables process design and process parameter optimization through simulation. The model also reveals the cause of wetting problems that may occur during the assembly process and provides a solution. Low cost assembly process will be achieved via optimizing an assembly process time and reducing a interconnect failure rate. This work will lead to a fundamental basis for better understanding the complex phenomenon of solder wetting during electronics assembly. Request This Paper
Abstract :: A chronically implantable retinal prosthesis is currently under development to restore useful vision to patients blind with degenerative retinal diseases such as age-related macular degeneration and retinitis pigmentosa.
These devices electrically stimulate the remaining healthy ganglion cells in the retina in response to wirelessly transmitted video data from outside the body, thereby effectively bypassing the dying photoreceptor cells. While these devices cannot be expected to provide the high acuity vision to which we are accustomed, they should restore the independence of some blind patients in performing many of the activities of daily living.
DEVELOPMENT AND ASSEMBLY OF A CHRONICALLY IMPLANTABLE RETINAL PROSTHESIS USING FLIP CHIP ON FLEX TECHNOLOGYThis paper reviews the prosthesis development at the Center for Innovative Visual Rehabilitation and presents the electronics module of the retinal implant including the assembly process used to produce the device. The miniaturized, high-density form factor and biocompatibility of the modules necessitates the use of parylene passivated flex circuitry with a dense circuit pattern. The primary ASIC is mounted using a gold wire stud bumped flip chip interconnect. Chip capacitors and resistors comprise both 0603 and 0402 body sizes. Secondary power and data coils are mounted on the mother flex circuit above the flex-to-flex connection to the stimulating electrode array. In order to ensure high yielding assemblies, a unique fixturing platform has been developed to maintain planarity of the flex circuit during solder paste print, component placement, solder reflow, and interconnect encapsulation. Request This Paper
Abstract :: This research focuses on flip chip interconnect systems consisting of wire stud bumps and solder alloy. Conventional gold (Au) wire stud bumps and new copper (Cu) wire stud bumps were formed on the chip by wire bumping. Cu wire studs were bumped by controlling the ramp of ultrasonic power to eliminate the occurrence of under-pad chip cracks which tend to occur with high strength bonding wire. Lead free 96Sn3.5Ag0.5Cu alloy was used to interconnect the wire studs and printed circuit board. A comparison is made with conventional eutectic 63Sn37Pb alloy and 60In40Pb alloy. A more stable solder connection was created when Cu wire stud bumps were used, compared with Au wire stud bumps. The improved stability is due to reduced intermetallic compound formation with the solder alloy.
Flip Chip Interconnect Systems Using Wire Stud Bumps and Lead Free SolderTest vehicles were assembled with two different Direct Chip Attachment (DCA) processes. When a conventional flip chip assembly and reflow was used, the lead free test vehicles exhibited process failure. On the other hand, when solder reflow and underfill cure were performed at the same time by using a high accuracy flip chip bonder, the reliability of lead free test vehicles in thermal shock improved. Request This Paper
Abstract :: Flip Chip Technology has begun to gain acceptance in electronics assembly due to its improved electrical performance and smaller size than most standard packages. The conventional flip chip process is not easily compatible with Surface Mount Technology (SMT) and therefore a lot of work has been done to improve the materials and processes involved. Based on this work, No Flow underfills were developed to make the flip chip process more transparent to SMT. Assembly and Cost modeling showed that no flow underfills could reduce cost by close to sixty percent when compared to conventional underfill processes and reduce the assembly time by close to fifty percent. The cost savings are most noticeable when the number of die per panel increases.
Utilization of No Flow Underfills for High Speed Flip Chip ApplicationsRequest This Paper
Abstract :: Chip Scale Package (CSP) technology is growing at a rapid pace since its emergence in the electronics manufacturing industry. As the solder joint size decreases, it has become apparent that underfill is necessary to meet certain reliability standards with CSPs, specifically drop testing. The need to underfill the CSP package has exerted the same drawbacks that are involved in flip chip assembly. No-flow underfills pose serious potential in this area as they can be incorporated into the standard SMT process with no post reflow processing. Most new materials simultaneously reflow and cure in the same reflow process used for standard SMT solder pastes. This work presents a reliability study of several commercial no-flow underfills and compares these CSPs to CSPs assembled without underfill and CSPs assembled with conventional fast-flow, snap-cure underfills. Samples were built using solder paste only, flux only, combinations of conventional underfill and solder paste or flux, and no-flow underfills. The reliability tests include liquid-to-liquid thermal shock (-40oC to 125oC) and board level drop tests (6-feet). Samples assembled with underfilled were benchmarked against the samples that were not underfilled. The CSP test vehicles consisted of a printed circuit board with 10 CSPs having 84 I/O and a 0.5-mm pitch. Through these tests, it has been determined that no-flow underfills can pass over 1000 cycles in liquid-liquid thermal shock, the typical standard for package/product qualification. Samples assembled with no-flow underfills also exhibited an increase in reliability during drop testing as compared to non-underfilled samples. The reliability data shows that no-flow underfill implementation on CSP increases reliability as compared to non-underfilled samples.
Implementation of No-Flow Underfills on Chip Scale PackagesRequest This Paper
Abstract :: Currently, underfill dispense processing is achieved through capillary action, making it a costly and time consuming process. As part of the Low Cost Next Generation Flip Chip Processing Program at Georgia Tech, an advanced flip chip assembly process was developed. This process eliminated the need for time consuming capillary flow processing, and integrates the simultaneous reflow and cure of the solder interconnect and polymer underfill. The advanced process results in a significantly lower assembly cost combined with reduced throughput time. Reduced throughput time and cost were achieved through the compression flow of the underfill material. The flow of the material governs assembly yield and reliability. Flow simulation studies of the placement process were conducted to characterize the compression flow of the underfill and predict void formation. Results yielded design guidelines that gave insight into process parameters such as the limits on underfill print height and underfill viscosity. The results indicated the initial limits of an overall process window for compression flow chip placement.
Compression Flow Modeling of Underfill Encapsulants for Low Cost Flip ChipRequest This Paper
Abstract :: Area array solder joints are difficult to visually inspect because solder joints are very tiny and covered by the chip. It may result in the increase of the interconnect defects passing the inspection step. Those defects become evident in later process steps or in the testing of the finished product. Since reworking of area array interconnects is very difficult and costly, interconnect yield is the crucial issue that determines the final product cost. The significance of interconnect yield becomes obvious as the demand on area array packages is growing. Therefore, it is essential to reduce the yield defects as close to zero as possible. The objective of this paper is to suggest design guidelines to implement Six Sigma, i.e., less than 3.5 defects per million in the assembly process of area array solder interconnect packages. For that purpose, the parameters impacting on interconnect yield are identified, the cause and effect relationships of design and process parameters to interconnect yield are analyzed, and the process design rules to statistically achieve Six Sigma are developed in general and explicit forms.
Design Guidelines to Implement Six Sigma in Assembly Process Yield of Area Array Solder Interconnect PackagesRequest This Paper
Abstract :: The Polymer Stud Grid Array (PSGA) package is a new and unique type of area array chip scale package that shows significant advantages over conventional package configurations by virtue of its high potential for miniaturization and process cost saving potential.This paper focuses on two key elements of PSGA technology which are: 1) developing a high throughput flip chip assembly process technology for PSGA-CSP configurations using existing Surface Mount Technology (SMT), and 2) qualifying the reliability performance of flip chip PSGA packages. The flip chip interconnection system evaluated is eutectic lead-tin solder. Various flip chip strategies are screened based on underfill materials and associated flip chip process technology. The underfill materials selected for evaluation are no flow reflowable, fast flow snap cure encapsulants, and high performance underfill systems. This work discusses issues related to developing a robust high throughput flip chip assembly process and presents preliminary reliability based on air-to-air thermal cycling (-55oC to 125oC) of the assembled PSGA Chip Scale Packages (CSPs).
Flip Chip Assembly Process Development, Reliability Assessment and Process Characterization For Polymer Stud Grid Array-Chip Scale PackageRequest This Paper
Abstract :: This paper presents a flip chip on board predictive reliability model. The model is intended to be used for the prediction of mean time to failure in air-to-air thermal cycle or liquid-to-liquid thermal shock. The model incorporates non-traditional predictors of performance such as the glass transition temperature of the underfill material, the metallization of the substrate bond pads and the non-dimensional quantity of UBM area to the wettable substrate bond pad area. Several regression techniques were used to determine the best predictors for reliability performance. The strongest predictors were incorporated into the model. A case study is presented to show the utility of the model. In addition, the effects of percent cure of the no-flow fluxing underfill were evaluated in terms of reliability performance.
Predictive Failure Model of Flip Chip on Board Component Level AssembliesRequest This Paper
Abstract :: The advent of no-flow fluxing underfills for Flip Chip on Board application has required a new investigation of optimal processing for increased reliability. This research provides a systematic development of optimal process parameters for four commercially available fluxing underfills. The impact of the dispensing pattern on void formation is determined. DOE1 includes dispense pattern at 3 levels, and speed at 2 levels. Metrics include yield, material voiding, and fillet shape. Low temperature cure is used to isolate the effects of dispensing by avoiding any volatility of a standard reflow cure. The impact of the placement process is determined in a second experiment, DOE2, involving placement force, speed, and dwell time at 2 levels. Metrics include yield, underfill voiding, solder voiding, and electrical yield. The results of these experimental studies are used to select an optimal placement process for each material. Reflow parameters are investigated using a parametric approach. The following parameters are varied at 2 levels individually off a baseline profile: Peak Temperature, Time > 183 C, Peak Ramp Rate, Soak Time, and Soak Temperature. The results of these initial studies will be used to choose an optimal process for each material. Test boards were assembled according to the optimal process for each material, and AATC thermal cycling test was performed.
Evaluation, Optimization, and Reliability of No-Flow Underfill ProcessRequest This Paper
Abstract :: Dramatic changes are underway in the computer, telecommunication, automotive, and consumer electronics industries. Changes that demand common and pervasive requirements for active assemblies such as: (1) ultra-low cost, (2) thin, light, and portable, (3) high performance, and (4) diverse functionality. The biggest bottleneck to achieving these is typically not the ICs but rather the electronic packaging. System in Packaging (SIP) is a packaging solution that provides the high performance and high flexibility package architectures that meets the system demands.
Flip Chip Processing Solutions as used in System in Package ApplicationsSystem in packaging provides a unique packaging solution allowing designers to tailor high density and high performance electronic systems into application specific packages at costs far less than custom, system on a chip solutions. Depending on their application environment, SIPs provide for high levels of integration between interconnect levels, passive elements, optoelectronic, digital, and RF functions. To achieve this, the predominant chip to package interconnect strategies are die attach with wire bonds and flip chip interconnects on multi-functional high density interconnect substrates. Of particular interest are flip chip solutions as the need for high I/O’s, high performance and high speed has moved to the forefront in customer requirements. Flip chips provide increased I/O counts, improved electrical performance, reduced cost, and smaller size. In this paper flip chip interconnect technology is reviewed with particular emphasis on design for manufacturing for system in packages to insure high yield production. Factors such as substrate design guidelines, bump design guidelines, under bump metallization selection, interconnect materials selection, and underfill selection are discussed. In addition, reliability requirements and test methods are also reviewed. A case study on flip chip blue tooth module processing is presented Request This Paper
Abstract :: For miniature interconnection applications, innovative material systems based on gallium alloys offer potentially attractive alternatives over commonly used bonding materials, such as solders and conductive adhesives, without the reliability and environmental drawbacks. Gallium alloys are mechanically alloyed mixtures of a liquid metal and metallic powders, formed at room temperature which cure to form solid intermetallic interconnects. Through the course of this work, gallium alloys have been investigated for flip-chip interconnect applications. Specifically, this paper presents the results of a preliminary feasibility study demonstrating the applicability of gallium alloys as flip-chip on laminate interconnect materials. The topics covered include the test vehicle assembly process, reliability screening results, preliminary failure mode analysis, and interconnect microstructure analysis.
Gallium Alloy Interconnects For Flip-Chip Assembly ApplicationsTo demonstrate preliminary feasibility and application, gallium alloyed with copper and nickel was used as micro-miniature interconnects between bare silicon chips and printed circuit boards. This initial study shows feasibility of such interconnects and the reliability tests demonstrate sufficient cyclic fatigue reliability in the presence of underfill material. Moreover, through the course of this work a new micro-dispensing technology for gallium alloys was developed which leverages existing industry infrastructure. This initial study represents a significant advancement in microelectronic interconnect materials unveiling the potential for an innovative lead-free interconnect alternative. Request This Paper
Abstract :: The compatibility of flux and underfill material systems significantly contributes to the formation and growth of process-induced defects and further influences flip chip reliability. Various no-clean fluxes, along with a water-soluble flux used as the baseline, are tested with two fast flow, snap cure underfills. Liquid-to-liquid thermal shock and temperature and humidity tests are conducted to evaluate the reliability of each flux-underfill material system. The failure modes, specifically underfill delamination, solder fatigue, and die cracking, are identified and analyzed. The correlation among process manufacturing defects, failure modes, and long-term reliability are determined. Understanding these failure modes will further enable and facilitate the implementation of low cost, high yield flip chip processing in standard surface mount technology.
Flux-underfill compatibility and failure mode analysis in high yield flip chip processingRequest This Paper
Abstract :: Over the past several years, flip chip technology has been heavily focused on developing and refining the next generation of flip chip assembly processes and reliability; yet, little attention has been paid to the environmentally conscious aspects of manufacturing and high process throughput. With legislation pending on the use of lead in Europe and Japan and to limit environmental impact, flip chip technology must address new ways to meet safety and environmental requirements for the materials and processes used during assembly. The focus of this research is to characterize and implement environmentally conscious low cost flip chip material systems and processing, using two lead-free-solder interconnect systems and microvia halogen-free substrates, thus minimizing the environmental impact. The objective is to ensure that environmentally friendly materials are selected, along with acceptable process technology for all materials as well as for the flip chip assembly.Processing and Reliability of Flip Chip with Lead-Free Solders on Halogen-Free Microvia SubstratesAn assembly process for environmentally conscious low cost flip chip assembly to microvia laminate substrates will be presented, based on a fully integrated high speed flip chip assembly line. The process includes the flux application, chip placement, reflow process, and underfill processing. Flux and underfill material compatibility will be discussed, and data will be presented analyzing the quality of the solder joint formation and underfill adhesion to halogen-free solder masks. 204-µm pitch peripherally bump, daisy chain test chips with edge lengths of 5 mm and 10 mm respectively are used. Comprehensive reliability results are presented, comparing the two lead-free to tin/lead eutectic interconnect systems. The chips are assembled on microvia substrates with electroless nickel/immersion gold surface finish, comparing conventional to halogen-free FR-4 and solder masks. A fast flow snap cure underfill, qualified for use with eutectic tin/lead joints on conventional FR-4, is used for both board types. Reliability results from air-to-air thermal shock testing are presented, comparing lead-free to eutectic interconnect systems mounted on conventional and halogen-free microvia substrates. Process and failure mode analysis are presented, based on x-ray inspection, C-SAM analysis, and assembly cross sections. Request This Paper
Abstract :: As advanced microelectronics systems evolve, it is forcing manufacturers to provide solutions for processing problems that have continually faced the industry. These problems exist due to the demand to provide distinctly different products each new generation, which requires the use of innovative miniaturization technologies, such as flip chip and chip scale packaging. New materials are being introduced to further improve the processing speed of flip chip on board. These materials are no flow underfills. Properly formulated, these underfills can significantly decrease manufacturing cost by eliminating the fluxing process, the underfill flow process, and the underfill cure process. This work evaluates the processing and reliability of no-flow underfill materials on a number of test vehicles and under a variety of test conditions. Failure mode analysis of flip chip structures using no flow underfills is also presented. Six test vehicles and four reliability tests were used to evaluate and analyze the reliability performance of several commercial no-flow underfill materials. Different test vehicles were used to evaluate the effect of varying chip size, interconnect density, pad surface finish metallization, and soldermask opening design. Accelerated reliability tests performed included liquid/liquid thermal shock (LLTS), air/air thermal cycling (AATC), moisture sensitivity preconditioning, and temperature humidity aging (TH). Materials tested in this work demonstrated the ability to survive 1000 cycles in LLTS and AATC without failure, 1000 hours of TH and J standard level three preconditioning. A number of unique failure modes are identified including bulk underfill cracking, fillet cracking, solder interconnect fatigue cracking and underfill interfacial delamination.
Implementation of no Flow Underfill Materials for Low Cost Flip Chip AssemblyRequest This Paper
Abstract :: As a concept to achieve high throughput low cost flip chip on board (FCOB) assembly, a process development and reliability assessment is underway. This process implements next generation flip chip processing based on large area underfill printing/dispensing, integrated chip placement and underfill flow, and simultaneous solder interconnect reflow and underfill cure. Reported in this work is the assembly of a series of test vehicles to evaluate the reliability of no-flow underfill materials. The reliability performance of four underfill materials is evaluated using six test vehicles. Accelerated reliability tests performed on the test vehicles included liquid/liquid and air/air thermal cycling, autoclave, and J-STD-020 Level 3 preconditioning. No-flow underfill materials tested in this work have demonstrated the ability to survive in excess of 1000 cycles of liquid/liquid thermal shock, survive more than 100 hours of autoclave, and pass J-STD-020 Level 3 preconditioning.
Low Cost Flip chip processing utilizing No flow underfill materialsRequest This Paper
Abstract :: Advanced electronics assembly based on direct attachment of semiconductor devices to printed circuit boards is a rapidly growing technology. Direct chip attach (DCA) or flip chip on board (FCOB) processing typically requires application of underfill materials in order to achieve adequate reliability for commercial electronic applications. Unfortunately, flip chip on board processing has yet to become a low cost, high throughput process compatible with high volume electronics packaging and high volumer surface mount processing. In order for FCOB processing to be high volume electronics packaging and SMT compatible, innovative techniques for underfill processing are required. This paper analyzes underfill processing in order to assess manufacturablity in terms of productivity and cost. In particular, four techniques for underfill processing are analyzed including capillary flow, vacuum assisted capillary flow, injection flow, and compression flow processing.
Manufacturing analysis of underfill processing for low cost flip chip assemblyRequest This Paper
Abstract :: No-Flow underfill process has been widely accepted as a key technology to implement low-cost, high-throughput flip chip on board (FCOB) assembly because of the elimination of processing steps such as flux application, flux residue cleaning, capillary underfill flow and secondary thermal curing of the underfill. While feasibility tests for the low-cost, high-throughput flip chip assembly based on no-flow underfill over a wide range of flip chip configurations are underway, unfamiliar process defects that have not been observed in the conventional capillary flow process are newly emerging. Of those new process defects, “chip floating” over the board surface after chip placement process is a critical issue that may significantly impact process yield when process variables are not properly controlled. It was found that much of the yield losses observed post reflow is attributed to the “chip floating”. In order to understand the underlying physics of the floating phenomena and predict process variables to eliminate the process defects, a process model has been developed. The critical process variables include chip placement speed, chip placement force, dwell time, deposited underfill mass and underfill material properties such as viscosity, density, surface tension, wetting speed on the board, etc. A test chip and board was made such that chip floating over the board can be detected by testing the electric continuity of the path connecting the chip and board via the solder bumps. The effects of the critical process variables on the chip floating are investigated by a series of experiments and the results are compared to the theoretical model prediction for the model validation.
No-Flow Underfill Process Modeling and Analysis for Low Cost, High Throughput Flip Chip AssemblyRequest This Paper
Abstract :: During the reliability assessment of a flip chip on board assembly (FCOB) by environmental stress tests, the physical characteristics of the field operating conditions are not sufficiently addressed. The failure mechanisms active at the environmental stress test conditions may not be dominant at the service operating conditions. The magnitude and intensity of thermomechanical stresses experienced by a FCOB at service conditions are different from those in the environmental stress tests, which result in discrepancies between dominant failure modes in the field operating conditions and accelerated life test conditions. Driven by the non-field failure modes, design modifications and process improvements during the prototyping stage may be misled. A “service field-oriented reliability assessment” methodology is introduced in this paper to address this issue by using a power cycling technique. The associated experimental power cycling system for FCOBs field reliability assessment is developed in this research. The test vehicles are assembled using fine pitch flip chips and high-density interconnect (HDI) substrates. The in-situ continuities of individual Kelvin solder bumps and daisy chains of the FCOB assemblies are investigated during the power cycling tests. The physical failure modes are revealed by acoustic microscopy, cross sectioning and scanning electron microscopy. “Design for field reliability” is then achievable by the effective design modifications and manufacturing process improvements at the prototyping stage.
Reliability Assessment of Flip Chip on Organic Board Using Power Cycling TechniquesRequest This Paper
Abstract :: Fluxing underfill materials are widely used in electronics manufacturing to improve reliability performance. The prevailing process of applying fluxing underfill is by dispensing the desired volume onto the printed circuit board with optimized patterns. The underfill cure is accomplished concurrently with solder joint formation in the reflow process. Even though the processing time of applying underfill material by this method is much shorter than that of the conventional capillary flow underfill process, the processing time of underfill dispensing is much longer than other process steps (e.g., printing, chip placement, reflow, etc). Besides the long processing time, the underfill dispensing process requires complicated and expensive dispensing machines, which increase the manufacturing cost. In this research, an innovative dispenseless fluxing underfill process and the associated module have been developed to achieve high-speed SMT compatible underfill processing [1]. The underfill application and chip placement are integrated into one process step that is accomplished by one placement machine. The prototyping of flip chip on board assemblies utilizing this innovative process shows dramatically reduced processing time. This invention enables remarkable cost savings from shortening processing time and eliminating the capital cost associated with underfill dispensing machines. The developed process and module are fully compatible with the current SMT electronic manufacturing infrastructure. It provides a high-speed and cost-effective solution for flip chip, CSP, and BGA electronic packaging assembly.
A Low Cost SMT Compatible Underfill Process for Advanced Chip AssemblyRequest This Paper
Abstract :: As advanced microelectronics systems evolve, it is forcing manufacturers to provide solutions for processing problems that have continually faced the industry. These problems exist due to the demand to provide distinctly different products each new generation, which requires the use of innovative miniaturization technologies, such as flip chip and chip scale packaging. New materials are being introduced to further improve the processing speed of flip chip on board. These materials are no flow underfills. Properly formulated, these underfills can significantly decrease manufacturing cost by eliminating the fluxing process, the underfill flow process, and the underfill cure process. This work evaluates the processing and reliability of no-flow underfill materials on a number of test vehicles and under a variety of test conditions. Failure mode analysis of flip chip structures using no flow underfills is also presented. Six test vehicles and four reliability tests were used to evaluate and analyze the reliability performance of several commercial no-flow underfill materials. Different test vehicles were used to evaluate the effect of varying chip size, interconnect density, pad surface finish metallization, and soldermask opening design. Accelerated reliability tests performed included liquid/liquid thermal shock (LLTS), air/air thermal cycling (AATC), moisture sensitivity preconditioning, and temperature humidity aging (TH). Materials tested in this work demonstrated the ability to survive 1000 cycles in LLTS and AATC without failure, 1000 hours of TH and J standard level three preconditioning. A number of unique failure modes are identified including bulk underfill cracking, fillet cracking, solder interconnect fatigue cracking and underfill interfacial delamination.
Implementation of no Flow Underfill Materials for Low Cost Flip Chip AssemblyRequest This Paper
Abstract :: Over the last several years, higher density flexible substrates have been introduced into high volume electronics assembly. As with any new technology, there are new challenges that arise in processing, reliability testing, material selection, and even fixturing. One of the main assembly issues with laminate structures is warpage due to the CTE mismatch between the laminated materials. The goal of this research was to utilize moiré techniques to investigate out of plane deformation of a 35mm TBGA component while in a reflow profile. The moiré analysis gave the out of plane deformation as a function of time and temperature for the test vehicles used throughout the experimentation.
Thermally Induced Out of Plane Deformation Analysis for a Flip Chip on Flex 35mm TBGAThere are several reasons for PWB or substrate warpage: the inherent CTE mismatches of the substrate building blocks, the transient temperature difference in the laminated substrate materials, and the rigidity of the substrate. Warpage from all of the above causes could affect flip chip attachment yield for first level interconnects. Warpage could cause misalignment between the die and the substrate and/or prevent the solder balls from making contact with the substrate flip chip pads during reflow, therefore the deflection of the substrate at reflow temperatures should be well understood for proper reflow process characterization. This out of plane deformation experienced in the reflow soldering process was investigated experimentally and studied via moiré techniques. The output from the moiré analysis gave real time flatness measurements of the substrates and aided in the development of a robust reflow process that resulted in yields of 98% or greater for a wide range of fluxes. Request This Paper
Abstract :: Direct chip attach packaging technologies are finding increasing application in electronics manufacturing particularly in telecommunications and consumer electronics. In these systems, bare die with bumped interconnect bond pads are assembled in a flip chip configuration (i.e., active face down) directly to low-cost organic substrates. In the current work, thermal management of three direct chip attach technologies is investigated. Experimental measurements are conducted exploring the junction-to-ambient thermal resistance and thermal dissipation paths for three interconnect technologies including solder attach, anisotropic adhesive attach, and isotropic adhesive attach. A first order chip-scale thermal design model is developed for flip chip assemblies exhibiting good agreement with the experimental measurements.
Thermal Dissipation Analysis in Flip Chip On Board and Chip On Board AssembliesRequest This Paper
Abstract :: Interest in using 0201 packages has increased greatly recent years due to the growth of the portable or hand held sectors of the electronics industry and miniaturization trends in consumer and commercial products. Other areas that 0201s are gaining influence include the RF applications and system in a package (SiP). A lot of research has been done to determine the board design considerations for 0201 processing, but work also needs to be done to determine the process window.
Processing Strategies for High Speed 0201 ImplementationInitial data presented last year showed a number of significant factors in the printing, placement, and reflow processes. From that study, the individual process steps showed that certain design and manufacturing parameters can have a huge effect upon total process defects. Presented in this paper is the data from those studies as well as the data gathered after a large evaluation run in which many components were processed. Studied process parameters were broken out by individual process steps initially, and then studied over the entire process. Some of the process parameters that were examined were stencil manufacturing method, print force, print speed, and stencil wipe frequency for the printing process and reflow atmosphere, profile shape, and ramp rate for the reflow process. From these studies, a reliable process window was obtained for a high speed 0201 assembly process that was proven to provide a 17 DPM assembly yield. Request This Paper
Abstract :: The use of 0201 packages is increasing from year to year as the industry continues to drive towards smaller, lighter, faster products. Many military applications are demanding miniaturized, high reliability designs to improve field performance and to reduce size and weight. An array of ten 0201s takes up almost 1/3 the area compared to 0402s. Therefore, components can be grouped tighter together to reduce board size and decrease weight while meeting harsh environment reliability requirements. The main challenges with the introduction of 0201 components in designs are that the key design factors for manufacturability are relatively unknown in the design community and confidence in the process window and its stability are unknown in the manufacturing sector since the process windows for 0201s do not scale from that of 0402s. This paper focuses on the a comprehensive analysis of the 0201 process, 0201 assembly reliability, and 0201 design for manufacturability factors to provide streamline introduction of miniaturized, high reliability COTS assemblies. Design factors studied include pad design, pad shape, pad pitch, pad spacing, ground plan effects, via-in-pad, feed trace width, component proximity, heat sinking effects, etc. Studied process parameters were broken out by individual process steps initially, and then studied over the entire process. Some of the process parameters that were examined were stencil manufacturing method, print force, print speed, and stencil wipe frequency for the printing process and reflow atmosphere, profile shape, and ramp rate for the reflow process. Robust design for manufacturing guidelines were developed and a reliable process window was obtained for a high speed 0201 assembly process that was proven to provide less than a 100 DPM assembly yield for both eutectic lead tin and lead free solder assemblies. Reliability performance of 0201 assemblies has also proven robust exhibiting high reliability in temperature humidity, air-to-air thermal cycling, and vibration environmental stress tests.
Designing an 0201 Assembly Process for High Yield and ReliabilityRequest This Paper
Abstract :: The introduction and use of smaller component packaging in electronic assemblies is driven by the need to reduce the overall product size while increasing functionality and performance. One of the more popular emerging package technologies is the 0201 discrete package. Shrinking component package sizes present numerous process challenges for electronics manufacturers and equipment suppliers. An SMT assembly process research facility in Norcross, Georgia undertook a project to develop a stable and reliable 0201 assembly process. A major challenge for the R&D facility was finding an AOI system capable of making the process measurements necessary. The researchers selected a 3D AOI system capable of both solder paste volume and component placement accuracy measurements. The system was used extensively in the 0201 process development study and the researchers relied upon the measurement data to draw many important conclusions about the process. The purpose of this paper is to present the performance of the developed process and the performance of the AOI system based on the results of the development project.
Process Capability Case Study on 0201 Processing Utilizing 3D Automated Optical InspectionRequest This Paper
Abstract :: The use of 0201 packages is increasing from year to year as the industry continues on its drive to smaller, lighter, faster. An array of ten 0201s takes up almost 1/3 the space of an array of 0402s. Therefore, components can be grouped tighter together to reduce board size. The main problem with the introduction of 0201 components is that the process window decreases as the size of the component decreases. An 0201 component has been shown to have ten times the likelihood to tombstone when compared to a 1206 and almost 2 ½ times as likely to tombstone as compared to an 04021. For this reason, a lot of attention must be paid to the design and processing of 0201 components for surface mount assembly.
Designing a High Yield 0201 Assembly Process for New Product IntroductionIn general, it has been found that the static factors (i.e. board and stencil design) have a much larger effect on the number of defects than the dynamic factors of the assembly process (i.e. print parameters, placement parameters, and reflow parameters). Some dynamic factors do have a large impact upon the assembly process (i.e. air versus nitrogen environment in the reflow), but overall the static design factors have a much greater impact upon the number of defects. Over the course of the study, the optimum assembly parameters were found and the effect of the design parameters on these assembly parameters will be shown in terms of defect per million numbers. Presented in this paper is the data from those studies as well as the data gathered after large evaluation runs in which many components were processed. Studied process parameters were broken out by individual process steps initially, and then studied over the entire process. Some of the process parameters that were examined were print force, print speed, and stencil wipe frequency for the printing process and reflow atmosphere, profile shape, and ramp rate for the reflow process. From these studies, a reliable process window was obtained for a high speed 0201 assembly process that was proven to provide a DPM of less than 200. Request This Paper
Abstract :: Microsystem packaging research is a burgeoning field focused on overcoming challenges associated with the commercialization of MEMS (Micro-Electro-Mechanical Systems) and other similar devices. Two pressing challenges are the reduction of package size and package cost, topics addressed by this work. To decrease package size a process is developed for the fabrication of high-aspect-ratio, through-wafer conductive vias. Combined with direct-chip-attach techniques, these vias allow for device-scale packaging of microsystems and are compatible with state of the art surface mount technology such as flip chip assembly. To minimize package cost a generic, wafer-level packaging architecture was devised based on reconfigurable silicon components. This approach allows a standard package to serve a wide variety of applications. It also decouples the packaging and device fabrication processes, letting modifications be made to either process independently. Low temperature bonding methods were used to join package components, permitting integration of driving circuitry on the microsystem die. The reconfigurable architecture allows standard package components to serve a wide variety of applications. The same packaging scheme also permits a controlled exploration of the functional impact of non-hermetic microsystem encapsulation.
Modular, Device-Scale, Direct-Chip-Attach Packaging For MicrosystemsRequest This Paper
Abstract :: This paper describes the development of a chip scale microelectromechanical system (MEMS) carrier compatible with modern surface mount assembly. Such a package could facilitate the commercial implementation of many MEMS devices currently feasible only as prototypes. In order to achieve the project goals, work focused on the reduction of MEMS package volume and on the incorporation of solder interconnect technology. The design integrated advances in the fields of MEMS fabrication and microelectronics packaging. A through-wafer electrical interconnect structure was developed in order to permit "face-up" device orientations and to minimize the package footprint. An interchangeable polymer assembly system and configurable cap structure allowed the package components to be combined in a modular fashion. Such flexibility should permit this one package architecture to serve the needs of a variety of MEMS applications. All processing and assembly was conducted at the wafer level after which a standard dicing process singulated individual packages. Conducting unit operations at the wafer level simplified much of the packaging process flow by alleviating alignment, bonding and handling concerns. The resulting packages were fully compatible with high-throughput surface mount equipment.
A Modular, Chip Scale, Direct Chip Attach Mems Package: Architecture and ProcessingRequest This Paper
Abstract :: There are many challenges currently hindering the commercialization of MEMS and microsystems, particularly those of reducing package cost and package size. Other concerns include microsystem release, hermeticity requirements, contamination and thermal hierarchy. The disproportionately high package to device cost ratio is largely due to the use of packaging solutions that are customized for a given microsystem. This practice is frequently adopted because different devices operate in varied environmental conditions. To find a generic package, which allows controlled interaction with the environment that a given microsystem is intended to sense and affect, is a significant challenge. An alternate approach that provides substantial savings and improved flexibility is the use of a modular, miniaturized packaging architecture. It is possible to build packages to serve an extensive range of microsystem applications by simply reconfiguring basic components. Challenges and Solutions for Packaging MEMS and MicrosystemsIn addition to introducing the common practices in microelectronics packaging and reviewing two key challenges of MEMS packaging, this paper will review one particular packaging strategy based on the development of a modular, near-hermetic, direct-chip-attach, MEMS-scale microsystem package. Such a package could increase the commercial viability of microsystems while acting as a flexible platform for progressive research in the area of non-hermetic packaging. Request This Paper
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