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Q & A: implementation challenges of Lead-free solder in Flip Chip and CSP ApplicationsSMT Magazine, July 30, 2003Q: Our company has been producing underfilled flip chip-on-board and CSP assemblies for the past few years with good success. With pending regulations and the emerging demand for lead-free electronics, we are looking into implementing lead-free solder for our flip chip devices. What are some factors that need to be considered when launching a lead-free flip chip or lead-free CSP product? A: It is important to note that a shift to lead-free soldering is not a drop-in process. Before starting this type of project, it is important to note several of the key considerations for the process: lead-free alloy selection, flux, underfill and thermal profiling, to name a few. The selection of solder is especially critical with flip chip and CSP, where the solder plays an amplified structural role. A drop-in replacement to eutectic SnPb is no longer expected to appear as the global "standard" alloy. However, consumer electronics companies outside Japan seem to have agreed on the SnAgCu systems, with the alloying elements ranging from 3.0 to 4.7 percent Ag and 0.5 to 3.0 percent Cu. The melting temperature of the various alloy compositions do not vary much; they are between ~217° and 221°C. The stipulation of higher peak reflow temperatures will significantly impact the flux and flux residue. The materials that provide the most consistent yields and the highest reliability when processing flip chips and CSPs are those fluxes that have the lowest amount of residue without decomposing during the elevated reflow temperatures, causing interconnect yield loss. Optimization of the flux amount is important because interconnect formation can be inconsistent at elevated reflow temperatures required for lead-free solders. Excessive flux adversely affects reliability due to residues and underfill compatibility. With the lower surface energies of lead-free solders, insufficient flux amounts can lead to opens and/or poor solder joint formation. The reliability of flip chip and CSP devices is highly affected by the flux/underfill compatibility. Studies show that incompatibility of a flux/underfill combination results in a loss of adhesion, which in turn accelerates the cyclic fatigue due to the CTE mismatch. Particular attention should be paid to selection of compatible fluxes that can survive the elevated lead-free reflow profiles required. The level of underfill adhesion to all surfaces in the flip chip and CSP system is what dictates reliability of the assemblies. This includes the solder mask, exposed bare board, solder, chip passivation and any flux residues that may be present. In the case of lead-free solders, there is a need to examine the difference in underfill adhesion as compared to the known good adhesion to SnPb alloy joints. The elevated reflow temperatures can cause further breakdown and decomposition of the flux chemistry leading to residues that are not soluble in liquid underfills. The ultimate effect is loss of underfill adhesion surrounding the solder interconnect, propagation of delamination, and the rapid fatigue failure of the solder interconnects. For lead-free soldering, reflow profiling is critical for developing a temperature profile that allows robust solder interconnect formation yet also keeps as low a peak temperature as possible. The liquidus temperature of the lead-free alloy used for flip chip and CSP assembly is ~217°C to 221°C. In contrast, the liquidus temperature of 63Sn-37Pb is 183°C - a 34°C difference. In the beginning it will be important to closely monitor this phase of the process and ensure the reflow process maintains a Cpk value of 1.33 or higher with respect to the key reflow profile variables of peak temperature, time above liquidus, soak time, soak temperature, and ramp rate based on the selected flux and solder paste materials. Daniel F. Baldwin, Ph.D. is the president of Engent Inc., Norcross, Ga. Link to article on SMT Magazine For more information about Engent, Inc, please contact us at:
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